1.Both are Hardware description languages 2.Verilog is case sensitive where as VHDL is not 3.Verilog has very simple data types where as VHDL allows to create more complex data types 4.Verilog does not support library management while VHDL does 5.In VHDL Functions and procedure may be placed in a package so that they are available to any design-unit that wishes to use them.
There is no concept of packages in Verilog. Functions & procedures used within a model must be defined with in the module. To make functions and procedures generally accessible from different module statements, those functions and procedures must be placed in a separate file and include them using the `include directive.
1.Both are Hardware description languages
ReplyDelete2.Verilog is case sensitive where as VHDL is not
3.Verilog has very simple data types where as
VHDL allows to create more complex data types
4.Verilog does not support library management
while VHDL does
5.In VHDL Functions and procedure may be placed
in a package so that they are available to
any design-unit that wishes to use them.
There is no concept of packages in Verilog.
Functions & procedures used within a model must be defined with in the module. To make functions and procedures generally accessible from different module statements, those functions and procedures must be placed in a separate file and include them using the `include directive.
you can find more about Verilog and VHDL using this link
ReplyDeletehttp://www.angelfire.com/in/rajesh52/verilogvhdl.html