Latch-up is a low resistance connection between substrate or tub and power supply rails.
It is possible to design chips that are latch-up resistent where a layer of insulating oxide (called trench) surounds both NMOS and PMOS transistors. This breaks the parasitic SCR structure between PMOS & NMOS.
Most silicon-on-insulator(SOI) devices are inherently latch-up resistant.
Latch-up is a low resistance connection between substrate or tub and power supply rails.
ReplyDeleteIt is possible to design chips that are latch-up resistent where a layer of insulating oxide (called trench) surounds both NMOS and PMOS transistors. This breaks the parasitic SCR structure between PMOS & NMOS.
Most silicon-on-insulator(SOI) devices are inherently latch-up resistant.