Monday, October 3, 2011

6. Any four differences between wire and reg in Verilog?

1 comment:

  1. WIRE:
    1.Physical connection between elements.
    2.It is used to assign value by a continuous
    assignment or a gate output
    3.Wire can not hold or store the value when there is no physical connection.
    4.Default value is ' Z '

    Reg:
    1.It representa a data storage element.
    2.Assigns values only within an 'always' or 'initial' procedural assignments
    3.Reg can hold the value even when there is no physical connection
    4.Dafault value is ' X '

    ReplyDelete