Monday, October 3, 2011

1. Differentiate inter and intra statements Delays in Verilog with an example?

2 comments:

  1. Inter statement delay: It is the delay where the instruction execution is performed after the specified number of time steps. In the expression the values of b and c are sampled after the specified amount of delay and perform the addition and assign the result to the LHS immediately.
    #10 a = b+c ;
    Wait for 10 time units, sample the b and c values, perform addition, assign to ‘a’ immediately.
    Intra statement delay: Here the result of the evaluated expression is assigned to LHS after the specified number of time units.
    a = #10 b+c ;
    First sample b and c values, perform addition, wait for 10 time units, then assign the result to ‘a’

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    1. so basically both the statements are going to take 10 units of time + computational time. Except for the sequence of operation, both statements seem to work at the same time. Meaning they are similar except for the sequence of execution.

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