My IEEE paper

my paper published in IEEE

Please post important website links for DIGITAL

26.       Design 2x1 MUX using Transmission gates?

27.       What is the best way to cascade the pass transistors?

28.       Design D-latch using MUX?

29.       Explain logical, Electrical and parasitic efforts?

30.       Explain SRAM and DRAM (single cell diagram, applications and differences)?

23.       What are the limitations of Pass transistor? And what should be done to overcome them?

24. What are the limitations of Transmission gate? And what should be done to overcome them?

25.       Design 4x1 MUX using two and three 2x1 MUXs separately?

20. Explain Body effect or Body bias and what is this bias voltage for NMOS and PMOS transistors?

21.       What are sizes of PMOS and NMOS transistors in CMOS inverter and Transmission gate? And explain the reasons in both cases?

22.       What is the LATCH-UP problem and how to overcome it?

17.       What is FPGA? What are main blocks in it?

18.       Explain about V_IL, V_IH, V_OL, V_OH and Noise Margin?

19. Explain Body effect or Body bias and what is this bias voltage for NMOS and PMOS transistors?

14.       What is Master-Slave flip-flop and why it is used?

15. What if the PMOS and NMOS transistors are interchanged in a CMOS inverter?

16.       Explain the CMOS inverter transfer characteristic in detail with diagram?

11.       What is HOLD time? What happens if HOLD time constraint is violated?  What should be done to not to violate it?

12.       Explain about clock skew and clock jitter with timing diagrams (Including advantages and disadvantages of each)?

13.       Explain about clock skew and clock jitter with timing diagrams (Including advantages and disadvantages of each)?

9.       Write the Verilog code for D (latch and Flip-flop), SR (latch and flip-flop), JK flip-flop, T flip-flop with synchronous and asynchronous RESET, with and without ENABLE signals?

10.       What is SETUP time? What happens if HOLD time constraint is violated?  What should be done to not to violate it?

5. Any four differences between Verilog and VHDL?

6. Any four differences between wire and reg in Verilog?

7. Exchange the contents of two variables with and without using temporary variable in both Verilog and C?

8. Difference between synchronous and asynchronous RESETs?

3. Any four differences between BLOCKING and NON-BLOCKING statements?

4. Any four differences between Verilog and C?

1. Differentiate inter and intra statements Delays in Verilog with an example?

2. Explain continuous and procedural assignments in Verilog?

verilog tutorial

http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/index.html

ONLY ONE

DDFIGJDFKNDSFLKKNV;DN

middle east countries and their status